ECE_115C_Presentation

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# A 1.25GHz 113fJ 4-bit Absolute-Value Detector for use in Neural Spike Sorting

The goal of this project is to design a 4-bit “Absolute-value Detector” with the minimum energy and worst-case delay of 800ps. Here “delay” refers to the worst-case propagation delay and “energy” refers to total energy drawn from VDD for a given input probability distribution. You may use gate sizing and supply voltage scaling as variables.